| US 7,558,979 B2 | ||
| Methods for determining simultaneous switching induced data output timing skew | ||
| Ho-young Song, Gyeonggi (Korea, Republic of); Seong-jin Jang, Gyeonggi-do (Korea, Republic of); and Kwang-il Park, Gyeonggi-do (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (Korea, Republic of) | ||
| Filed on Aug. 01, 2005, as Appl. No. 11/194,180. | ||
| Claims priority of application No. 10-2004-0085088 (KR), filed on Oct. 23, 2004. | ||
| Prior Publication US 2006/0092717 A1, May 04, 2006 | ||
| Int. Cl. G06F 1/00 (2006.01); G06F 11/00 (2006.01) | ||
| U.S. Cl. 713—500 [713/501; 713/503; 370/508] | 4 Claims |
| 1. A data training method performed in a memory device which does not include an additional device for data training, the
method comprising:
(a) writing a predetermined data pattern to the memory device;
(b) reading a data pattern from the memory device; and
(c) determining a delay time in data transmission by measuring a delay time between the read data pattern and the predetermined
data pattern,
wherein a speed at which the predetermined data pattern is written to the memory device is less than a normal operating speed
of the memory device, and
wherein (b) the reading of the data pattern comprises:
(b1) operating the memory device at the normal operating frequency; and
(b2) reading the data pattern from the memory device at the normal operating frequency; and
wherein (b) the reading of the data pattern further comprises (b3) selecting a pin of the memory device which performs the
data training.
|