| US 7,558,939 B2 | ||
| Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor | ||
| Soumya Banerjee, San Jose, Calif. (US); Michael Gottlieb Jensen, Sunnyvale, Calif. (US); and Ryan C. Kinter, Sammamish, Wash. (US) | ||
| Assigned to MIPS Technologies, Inc., Sunnyvale, Calif. (US) | ||
| Filed on Mar. 08, 2005, as Appl. No. 11/75,041. | ||
| Prior Publication US 2006/0206686 A1, Sep. 14, 2006 | ||
| Int. Cl. G06F 12/00 (2006.01) | ||
| U.S. Cl. 711—205 [711/206; 711/207] | 77 Claims |
| 1. A hardware three-tiered translation lookaside buffer (TLB) apparatus in a multithreading microprocessor that concurrently
fetches and executes instructions of a plurality of threads, for providing virtual-to-physical address translation information
for a memory page in response to an instruction cache virtual fetch address for a selected one of the plurality of threads,
the apparatus comprising:
a third-level TLB, for caching virtual-to-physical address translation information for a plurality of memory pages for the
plurality of threads;
a second-level TLB, coupled to said third-level TLB, having a plurality of entries for caching said virtual-to-physical address
translation information for a subset of said plurality of memory pages cached in said third-level TLB; and
a first-level TLB for each of a respective one of the plurality of threads, each said first-level TLB having at least one
entry for caching virtual-to-physical address translation information only for said respective one of the plurality of threads.
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