| US 7,558,812 B1 | ||
| Structures for LUT-based arithmetic in PLDs | ||
| Ketan Padalia, Thornhill (Canada); David Cashman, Toronto (Canada); David Lewis, Toronto (Canada); Andy L. Lee, San Jose, Calif. (US); Jay Schleicher, Santa Clara, Calif. (US); Jinyong Yuan, Cupertino, Calif. (US); and Henry Kim, San Jose, Calif. (US) | ||
| Assigned to Altera Corporation, San Jose, Calif. (US) | ||
| Filed on Nov. 26, 2003, as Appl. No. 10/723,104. | ||
| Int. Cl. G06F 7/38 (2006.01) | ||
| U.S. Cl. 708—235 [326/38] | 12 Claims |
| 1. A programmable logic device (PLD) including a plurality of logic array blocks (LAB's) connected by a PLD routing architecture,
wherein at least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input
signals in a plurality of stages, the LE comprising:
a K input look-up table (“K-LUT”), the K-LUT configured to input the binary input signals at respective inputs of the K-LUT
and to provide, at a plurality of outputs of the K-LUT, respective binary result signals indicative of at least two of the
plurality of stages of the arithmetic combination of binary input signals;
an input line network including a network of input lines and an input multiplexer, the input lines configurable to receive
input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to
the K-LUT, wherein the input multiplexer is configured to receive input signals from at least one of the input lines and provide
output signals to the K-LUT, the input line network is configured to provide at least a first one of the input signals to
both a first K-LUT portion and a second K-LUT portion in a first state, and provide a first carry-in signal to the first K-LUT
portion and a second carry-in signal to the second K-LUT portion in a second state;
an output line network including a network of output lines and an output multiplexer, the output lines configured to receive,
from the K-LUT, output signals that represent the binary result signals and to provide the output signals to the PLD routing
architecture, wherein the output multiplexer selects an output signal at outputs of the K-LUT;
wherein:
the K-LUT includes a plurality of portions, each portion connected to the routing architecture via the input line network
to receive at least some of the input signals;
each of the plurality of portions of the K-LUT includes circuitry to generate the binary result signals indicative of a respective
separate one of the plurality of stages of the arithmetic combination of binary input signals; and
the input line network includes at least a first input multiplexer between the routing architecture and a first one of the
K-LUT portions and at least a second input multiplexer between the routing architecture and a second one of the K-LUT portions;
the input line network is configured to
in-the first state, provide at least the first one of the input signals to both the first K-LUT portion and the second K-LUT
portion, via the first input multiplexer and the second input multiplexer, respectively, and
in-the second state, instead provide the first carry-in signal to the first K-LUT portion and the second carry-in signal to
the second K-LUT portion, via the first input multiplexer and the second input multiplexer, respectively.
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