a playback signal detection circuit for detecting a playback RF signal from the optical recording medium;

a playback RF signal adjustment circuit for adjusting an amplitude of the playback RF signal, and improving jitters;

a clock generation circuit for generating a sampling clock that is synchronized with a period twice as long as a clock component included in the playback RF signal;

an AD converter for generating a digital RF signal by sampling an output signal of the playback RF signal adjustment circuit with the sampling clock;

a first offset correction circuit for correcting an offset component in an amplitude direction in the digital RF signal;

a phase sync control circuit for extracting phase error information from an output signal of the first offset correction circuit, and performing phase sync control of the sampling clock generated by the clock generation circuit, so as to bring the phase error information close to zero;

a digital adaptive equalizer for adaptively equalizing the output signal of the first offset correction circuit;

a second offset correction circuit for correcting an offset component in the amplitude direction which occurs in an output signal of the digital adaptive equalizer due to influence of the offset component that cannot be corrected by the first offset correction circuit;

an interpolation filter for receiving the output signal of the digital adaptive equalizer as an input signal, and generating a first demodulation preprocessing signal by delaying the input signal by a predetermined period of time, and a second demodulation preprocessing signal which is a signal missing in the time direction of the input signal;

said second offset correction circuit extracting offset information in the amplitude direction from the first demodulation preprocessing signal and the second demodulation preprocessing signal to correct the offset component in the amplitude direction of the output signal from the digital adaptive equalizer;

a jitter detection circuit for extracting jitter information from the first demodulation preprocessing signal and the second demodulation preprocessing signal; and

a data demodulation circuit for demodulating the first demodulation preprocessing signal and the second demodulation preprocessing signal to obtain a digital binary signal.