| US 7,558,148 B2 | ||
| Memory controller | ||
| Hiroshi Sukegawa, Tokyo (Japan); and Takeshi Nakano, Kawasaki (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jul. 11, 2007, as Appl. No. 11/776,037. | ||
| Claims priority of application No. 2006-194804 (JP), filed on Jul. 14, 2006. | ||
| Prior Publication US 2008/0052447 A1, Feb. 28, 2008 | ||
| Int. Cl. G11C 8/00 (2006.01) | ||
| U.S. Cl. 365—230.09 [365/185.17; 365/185.33; 365/185.02] | 20 Claims |
| 1. A memory controller which writes data in a first semiconductor memory including a plurality of memory cells, a first selection
transistor, a second selection transistor, a first select gate line, a second select gate line and a plurality of word lines,
the plurality of memory cells having current paths connected in series between a source of the first selection transistor
and a drain of the second selection transistor, each of the plurality of memory cells having a control gate and a charge storage
layer, the first and second select gate lines respectively connected to gates of the first and second selection transistors,
and the plurality of word lines respectively connected to the control gates,
the memory controller comprising:
a host interface which is configured to be connectable to a host apparatus and to be receivable of first data from the host
apparatus;
a second semiconductor memory which temporarily holds second data; and
an arithmetic unit which generates the second data in accordance with a state of the first semiconductor memory, temporarily
holds the second data in the second semiconductor memory, and writes, in the first semiconductor memory, the first data from
the host interface and the second data held in the second semiconductor memory,
wherein when writing the second data, the arithmetic unit does not select the word lines adjacent to the first select gate
line and the second select gate line, and selects the word line not adjacent to the first select gate line and the second
select gate line.
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