| US 7,558,141 B2 | ||
| Memory system, semiconductor memory device and method of driving same | ||
| Ryota Katsumata, Yokohama (Japan); Masaru Kidoh, Kawasaki (Japan); Hiroyasu Tanaka, Tokyo (Japan); Masaru Kito, Yokohama (Japan); Hideaki Aochi, Kawasaki (Japan); Yoshiaki Fukuzumi, Yokohama (Japan); and Yasuyuki Matsuoka, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Dec. 13, 2007, as Appl. No. 11/955,900. | ||
| Claims priority of application No. 2007-000745 (JP), filed on Jan. 05, 2007. | ||
| Prior Publication US 2008/0180994 A1, Jul. 31, 2008 | ||
| Int. Cl. G11C 7/14 (2006.01) | ||
| U.S. Cl. 365—210.1 [365/185.02; 365/185.2; 365/185.23] | 19 Claims |
| 1. A semiconductor memory device comprising:
a semiconductor substrate;
first select transistors formed on the surface of said semiconductor substrate;
first dummy transistors formed above said first select transistors;
a plurality of memory cell transistors formed above said first dummy transistors so as to extend in a direction perpendicular
to the surface of said semiconductor substrate, each of said memory cell transistor including an insulating layer having a
charge-accumulating function;
second dummy transistors formed above said memory cell transistors; and
second select transistors formed above said second dummy transistors; wherein a first potential is provided to the gate electrodes
of said first select transistors and the gate electrodes of said first dummy transistors and a second potential is provided
to the gate electrodes of said second select transistors and the gate electrodes of said second dummy transistors at the time
of write operation to write data to said memory cell transistors.
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