| US 7,558,126 B2 | ||
| Nonvolatile semiconductor memory device | ||
| Mikio Ogawa, Yokohama (Japan); and Katsuaki Isobe, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Dec. 21, 2007, as Appl. No. 11/963,000. | ||
| Claims priority of application No. 2006-345712 (JP), filed on Dec. 22, 2006. | ||
| Prior Publication US 2008/0158957 A1, Jul. 03, 2008 | ||
| Int. Cl. G11C 11/00 (2006.01) | ||
| U.S. Cl. 365—189.05 [365/230.03] | 10 Claims |
| 1. A nonvolatile semiconductor memory device, comprising:
a plurality of memory cell arrays including a plurality of memory cells arrayed, the memory cell being capable of storing
information in accordance with differences in threshold voltage;
a selection transistor connected to one end of said memory cell, respectively;
a bit line connected to said selection transistor;
a source line connected to said selection transistor; and
a source line driver configured to supply a source voltage at a certain level to said source line at the time of erasing,
wherein said source line driver includes a first transistor, a second transistor and a third transistor connected in series,
and an opamp;
wherein said first transistor has one end connected to one end of said second transistor, and said first transistor has the
other end connected to power supply,
wherein said third transistor has one end connected to the other end of said second transistor, and said third transistor
has the other end grounded,
wherein said second transistor has an input terminal connected to an output terminal of said opamp,
wherein said opamp has one input terminal supplied with a reference potential and the other input terminal connected to a
node between said first transistor and said second transistor,
wherein said node between said first transistor and said second transistor is connected to said source line.
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