| US 7,558,120 B2 | ||
| Semiconductor integrated circuit device comprising MOS transistor having charge storage layer and method for testing semiconductor memory device | ||
| Hideyoshi Takai, Tokyo (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Dec. 20, 2007, as Appl. No. 11/961,172. | ||
| Claims priority of application No. 2006-348004 (JP), filed on Dec. 25, 2006. | ||
| Prior Publication US 2008/0151661 A1, Jun. 26, 2008 | ||
| Int. Cl. G11C 16/06 (2006.01); G11C 16/04 (2006.01); G11C 29/00 (2006.01) | ||
| U.S. Cl. 365—185.22 [365/185.18; 365/201] | 15 Claims |
| 1. A semiconductor integrated circuit device comprising:
a semiconductor memory which includes a memory block having a plurality of memory cells and which tests the memory cells during
a test operation to determine whether or not the memory cells are acceptable; and
a test circuit which controls the test operation on the semiconductor memory, the test circuit including
a controller which consecutively increments a gate voltage of the memory cells and which controls the semiconductor memory
so as to read a data from the memory cells provided with the gate voltage on each memory block; and
a counter which measures, for the gate voltage which is incremented by the controller, the number of memory cells determined
to be defective depending to the result of reading the data, the controller determining the memory block to be defective when
the counter consecutively shows a count falling within a predetermined range during the variation in gate voltage.
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