a memory cell array that includes a plurality of NAND memory cell units each including a connection element having a plurality of electrically-rewritable memory cells;

a plurality of word lines that are connected to the plurality of memory cells;

a plurality of bit lines that are connected to the plurality of memory cells; and

a read-write control section that applies a voltage selectively to the plurality of word lines and the plurality of bit lines to perform writing, reading, or erasure of data into or from the plurality of memory cells,

wherein each of the plurality of NAND memory cell units includes a first select gate transistor connected between one end of the connection element and the bit lines and a second select gate transistor connected between the other end of the connection element and a source line; and

wherein the read-write control section sets a voltage level applied to word lines connected to the control gate electrodes of memory cells adjacent to the second select gate transistor, so that the voltage level becomes lower than a predetermined voltage level applied to other word lines connected to control gate electrodes of memory cells except the memory cells adjacent to the second select gate transistor.