| US 7,558,117 B2 | ||
| Nonvolatile semiconductor memory device | ||
| Hiroshi Maejima, Milpitas, Calif. (US); and Makoto Hamada, Mountain View, Calif. (US) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Aug. 30, 2007, as Appl. No. 11/847,854. | ||
| Prior Publication US 2009/0059670 A1, Mar. 05, 2009 | ||
| Int. Cl. G11C 16/04 (2006.01) | ||
| U.S. Cl. 365—185.18 [365/185.21; 365/185.22] | 20 Claims |
| 1. A nonvolatile semiconductor memory device capable of reading and verifying a cell with a negative threshold voltage by
biasing voltages of a source line and well line to a positive voltage, comprising:
a voltage control circuit which applies a select gate voltage obtained by adding the biased positive voltage to a voltage
set at a read time of a cell with a positive threshold voltage to a select gate at a read time and verify time for the cell
with the negative threshold voltage.
|