| US 7,558,113 B2 | ||
| Memory system and data writing method | ||
| Kazuya Kawamoto, Sagamihara (Japan); Yoshiyuki Tanaka, Yokohama (Japan); and Hiroshi Sukegawa, Tokyo (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Aug. 28, 2007, as Appl. No. 11/846,334. | ||
| Application 11/846334 is a continuation of application No. 11/193433, filed on Aug. 01, 2005, granted, now 7,376,012. | ||
| Claims priority of application No. 2004-225026 (JP), filed on Aug. 02, 2004. | ||
| Prior Publication US 2008/0043534 A1, Feb. 21, 2008 | ||
| Int. Cl. G11C 16/04 (2006.01) | ||
| U.S. Cl. 365—185.17 [365/185.09; 365/185.22] | 12 Claims |
| 1. A data writing method for use with a memory system including a NAND flash memory and a controller which controls the NAND
flash memory, in which data inputted from a host is stored in the NAND flash memory, the data writing method comprising:
carrying out a program operation to write data to a page of the memory cell array;
carrying out a verify-read operation of the written data;
judging based on a result of the verify-read operation whether or not failure occurs in writing data in any of the bits of
the page;
judging, if it is judged that failure occurs in writing data in any of the bits of the page, whether or not the number of
failed bits of the page is within a predetermined allowable number;
setting, if it is judged that the number of failed bits of the page is within the predetermined allowable number, a status
of Pass in a pseudo manner, ending the write operation and issuing a Ready signal; and
issuing a status read command from the controller to the NAND flash memory, upon receipt of the Ready signal, to determine
whether the status is Pass or Fail.
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