| US 7,557,849 B2 | ||
| Processor-controlled timing generator for multiple image sensors | ||
| Feng F. Pan, San Jose, Calif. (US); Yasu Noguchi, Sunnyvale, Calif. (US); and Young Kim, Fremont, Calif. (US) | ||
| Assigned to Mediatek USA Inc, San Jose, Calif. (US) | ||
| Filed on Oct. 11, 2004, as Appl. No. 10/963,494. | ||
| Prior Publication US 2006/0077275 A1, Apr. 13, 2006 | ||
| Int. Cl. H04N 3/14 (2006.01); H04N 5/335 (2006.01) | ||
| U.S. Cl. 348—312 [713/500; 327/144] | 9 Claims |
| 1. A circuit that generates a timing signal, the timing signal being for driving an image sensor, the circuit comprising:
a terminal;
a memory;
a processor that executes a program of instructions stored in the memory, wherein execution of the program causes the timing
signal to be generated and output from the terminal;
a horizontal timing generator that outputs the timing signal, the timing signal having signal edges that are adjustable to
within an amount of time, and wherein the processor is clocked by a clock signal having a period, the period of the clock
signal being substantially longer than the amount of time; and
a vertical timing signal generator that outputs a vertical timing signal, wherein the vertical timing signal generator comprises:
a plurality of counters; and
a register that stores a first count value, a second count value, and a third value, wherein the first count value identifies
a count associated with a first edge of the vertical timing signal, wherein the second count identifies a count associated
with a second edge of the vertical timing signal, and wherein the third value identifies a selected one of the plurality of
counters, wherein the processor writes the first count value, the second count value and the third value into the register.
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