| US 7,557,660 B2 | ||
| Power amplification device | ||
| Hiroyuki Tsurumi, Fujisawa (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Oct. 02, 2007, as Appl. No. 11/865,815. | ||
| Claims priority of application No. 2006-271073 (JP), filed on Oct. 02, 2006. | ||
| Prior Publication US 2009/0002072 A1, Jan. 01, 2009 | ||
| Int. Cl. H02H 7/20 (2006.01) | ||
| U.S. Cl. 330—298 [330/251] | 20 Claims |
| 1. A power amplification device comprising:
a BTL amplification circuit including a first amplification circuit and a second amplification circuit, the first amplification
circuit including a first output transistor having a current path with one end connected to a first power supply and the other
end connected to a first output terminal, a first power detection circuit which detects a power of the first output transistor,
a second output transistor having a current path with one end connected to a second power supply and the other end connected
to the first output terminal, and a second power detection circuit which detects a power of the second output transistor,
the second amplification circuit including a third output transistor having a current path with one end connected to the first
power supply and the other end connected to a second output terminal, a third power detection circuit which detects a power
of the third output transistor, a fourth output transistor having a current path with one end connected to the second power
supply and the other end connected to the second output terminal, and a fourth power detection circuit which detects a power
of the fourth output transistor;
a first comparator which compares output values of the first and fourth power detection circuits; and
a second comparator which compares output values of the second and third power detection circuits.
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