| US 7,557,624 B2 | ||
| Fractional digital PLL | ||
| Robertus Laurentius van der Valk, Capelle aan den Ijssel (Netherlands); Paulus Hendricus Lodewijk Maria Schram, Bergen op Zoom (Netherlands); and Johannes Hermanus Aloysius de Rijk, Rotterdam (Netherlands) | ||
| Assigned to Zarlink Semiconductor Inc., (Canada) | ||
| Filed on Nov. 15, 2007, as Appl. No. 11/940,458. | ||
| Claims priority of application No. 0622945.4 (GB), filed on Nov. 17, 2006. | ||
| Prior Publication US 2008/0122504 A1, May 29, 2008 | ||
| Int. Cl. H03L 7/06 (2006.01) | ||
| U.S. Cl. 327—156 [327/147] | 17 Claims |
| 1. A phase locked loop providing an output frequency that bears a fractional relationship to a frequency of an input signal,
comprising:
a controlled oscillator for generating the output frequency;
a feedback loop coupled to the output of the controlled oscillator and generating a feedback signal; and
a phase detector for comparing the input signal with the feedback signal to generate a phase signal for controlling the controlled
oscillator, said phase detector comprising a modulo N counter and a modulo M counter, where N and M are integers, one of said
counters receiving the input signal and the other of said counters receiving the feedback signal, and wherein the outputs
of said counters are applied to respective first and second scaling units, the first scaling unit applying an M/N scaling
factor, and the outputs of said scaling units being applied to a subtractor to provide the phase signal, whereby said phase
detector includes a scaling stage for scaling said phase information in the amplitude domain to produce the desired output
frequency.
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