US 7,557,623 B2
	Circuit arrangement, in particular phase-locked loop, as well as corresponding method
Ulrich Moehlmann, Moisburg (Germany); Timo Giesselmann, Hamburg (Germany); Edwin Schapendonk, Oss (Netherlands); Frank Brand, Harsefeld (Germany); and Leendert Albertus Dick Van Den Broeke, Malden (Netherlands)
Assigned to NXP B.V., Eindhoven (Netherlands)
Appl. No. 11/911,860 PCT Filed Apr. 13, 2006, PCT No. PCT/IB2006/051156 § 371(c)(1), (2), (4) Date Oct. 18, 2007, PCT Pub. No. WO2006/111899, PCT Pub. Date Oct. 26, 2006.
Claims priority of application No. 05103069 (EP), filed on Apr. 18, 2005.
Prior Publication US 2008/0204092 A1, Aug. 28, 2008
Int. Cl. H03L 7/06 (2006.01)

U.S. Cl. 327—156  [327/147]

10 Claims

1. A circuit arrangement, in particular a phase-locked loop for sub-clock or sub-pixel accurate phase-measurement and phase-generation, characterized by at least one phase measurement unit, in particular comprising at least one time-to-digital converter unit being provided with at least one input signal and at least one phase detector unit being provided with at least one output signal of the time-to-digital converter unit; at least one loop filter unit being provided with at least one output signal of the phase detector unit; at least one digital ramp oscillator unit or discrete time oscillator unit being provided with at least one output signal, in particular with at least one increment, of the loop filter unit, the status signal of at least one register unit of the digital ramp oscillator unit or discrete time oscillator unit being fed back as input signal to the phase detector unit; and at least one digital-to-time converter unit being provided with at least one output signal of the digital ramp oscillator unit or discrete time oscillator unit and generating at least one output signal, wherein the time-to-digital converter unit includes at least two shift register chains configured to process the input signal as an input of the shift register chains.