| US 7,557,614 B1 | ||
| Topology for a n-way XOR/XNOR circuit | ||
| Stefan Bonsels, Stuttgart (Germany); Martin Padeffke, Hildrizhausen (Germany); Tobias Werner, Weil im Schoenbuch (Germany); and Alexander Woerner, Boeblingen (Germany) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Jul. 15, 2008, as Appl. No. 12/173,569. | ||
| Int. Cl. H03K 19/21 (2006.01) | ||
| U.S. Cl. 326—55 [326/54] | 1 Claim |
| 1. A method for configuring a n-way XOR or XNOR circuit comprising:
providing a plurality of top stacks of PFETs, each top stack of PFETs including at least three PFETs electrically connected
between a high logic level and an output logic connection;
providing a plurality of bottom stacks of NFETS, each bottom stack including at least three NFETs electrically connected between
a low logic level and the output logic connection;
directly connecting a source or a drain of the outermost PFET in each top stack to a source or a drain of a corresponding
NFET in each bottom stack to generate inverted logic signals to be provided as gate inputs to other stacks;
inputting at least three input logic states to the stacks of PFETs to selectively connect or disconnect the output logic connection
to the high logic level based on the input logic states;
inputting at least three input logic states to the stacks of NFETs to selectively connect or disconnect the output logic connection
to the low logic level based on the input logic states; and
outputting a logic signal from the output logic connection.
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