| US 7,557,613 B2 | ||
| Scalable non-blocking switching network for programmable logic | ||
| Peter M. Pani, Mountain View, Calif. (US); and Benjamin S. Ting, Saratoga, Calif. (US) | ||
| Assigned to Advantage Logic, Inc., Mountain View, Calif. (US) | ||
| Filed on Jul. 16, 2008, as Appl. No. 12/174,080. | ||
| Application 12/174080 is a continuation of application No. 11/823257, filed on Jun. 26, 2007, granted, now 7,417,457. | ||
| Application 11/823257 is a continuation of application No. 11/218419, filed on Sep. 01, 2005, granted, now 7,256,614. | ||
| Application 11/218419 is a continuation of application No. 10/814943, filed on Mar. 30, 2004, granted, now 6,975,139. | ||
| Prior Publication US 2008/0272806 A1, Nov. 06, 2008 | ||
| Int. Cl. H03K 19/177 (2006.01) | ||
| U.S. Cl. 326—41 [326/47; 370/388] | 12 Claims |

| 1. An integrated circuit, comprising:
a permutable switching network (SN);
wherein the permutable SN comprises:
an (i−1)-th level of conductors of I[i−1] number of conductors, comprising (I[i]/D[i]) number of (I[i−1]/I[i])×D[i] number
of conductors, selectively coupled to each set of the D[i] number of sets of an i-th level of D[i] number of sets of conductors
of I[i] number of conductors, comprising D[i] number of (I[i]/D[i]) number of conductors, through I[i−1] number of switches,
wherein (I[i−1]/I[i])×D[i]>1, D[i]>1 for i=[1:L+1] where L≧1 and (I[L+1]/D[L+1])=Πi=[1:L] D[i]>2 where D[L+1]>2;
each conductor of the (i−1)-th level of conductors of I[i−1] number of conductors selectively coupled to one conductor of
each of the D[i] number of sets of the i-th level of D[i] number of sets of conductors of I[i] number of conductors through
a respective switch from each of the D[i] number of I[i−1] number of switches; and
each (I[i]/D[i]) number of I[i−1]/I[i])×D[i] number of conductors selectively coupled to one respective conductor of each
of the D[i] number of sets of conductors of the i-th level of D[i] number of sets of conductors of I[i] number of conductors
through (I[i−1]/I[i])×D[i] number of switches, wherein each of the D[i] number of sets of conductors has (I[i]/D[i]) number
of conductors.
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