| US 7,557,598 B2 | ||
| Method of inspecting quiescent power supply current in semiconductor integrated circuit and device for executing the method | ||
| Yuetsu Ochiai, Kanagawa (Japan); and Kentaro Yamamoto, Kanagawa (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Mar. 08, 2007, as Appl. No. 11/715,439. | ||
| Claims priority of application No. 2006-064501 (JP), filed on Mar. 09, 2006. | ||
| Prior Publication US 2007/0210824 A1, Sep. 13, 2007 | ||
| Int. Cl. G01R 31/02 (2006.01); G01R 31/26 (2006.01); G01R 31/08 (2006.01) | ||
| U.S. Cl. 324—765 [324/763; 324/522] | 8 Claims |
| 1. A method of inspecting a quiescent power supply current in a semiconductor integrated circuit, the method comprising:
(a) an ID information acquisition process for acquiring ID information of one of a plurality of semiconductor integrated circuits;
(b) a quiescent power supply current measuring process for measuring a quiescent power supply current value of the quiescent
power supply current in the one of the plurality of semiconductor integrated circuits;
(c) a measurement information storing process for storing the quiescent power supply current value and the ID information
in corresponding pairs;
(d) repeating the processes (a) through (c) for storing a plurality of measured quiescent power supply current values for
the plurality of semiconductor integrated circuits;
(e) a reference value determining process for determining a reference value on the basis of the plurality of measured quiescent
power supply current values stored in the memory; and
(f) a defect determining process, by comparing a stored quiescent power supply current value with the reference value, for
determining whether the semiconductor integrated circuit is defective or not.
|