| US 7,557,422 B2 | ||
| Semiconductor device with STI structure | ||
| Katsuya Ito, Yokkaichi (Japan); Hiroaki Tsunoda, Yokkaichi (Japan); and Takanori Matsumoto, Yokkaichi (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jul. 27, 2007, as Appl. No. 11/829,521. | ||
| Application 11/829521 is a division of application No. 11/086379, filed on Mar. 23, 2005, granted, now 7,265,022. | ||
| Claims priority of application No. 2004-085052 (JP), filed on Mar. 23, 2004. | ||
| Prior Publication US 2007/0262394 A1, Nov. 15, 2007 | ||
| Int. Cl. H01L 29/00 (2006.01) | ||
| U.S. Cl. 257—510 [257/374; 438/426] | 6 Claims |
| 1. A semiconductor device comprising:
a semiconductor substrate including a memory cell region and a peripheral circuit region;
a first trench formed in the memory cell region, the first trench having a first depth and a first opening width; and
a second trench formed in the peripheral circuit region, the second trench including a pair of bottom edge portions and a
bottom middle portion located between the bottom edge portions, the second trench having a second opening width that is larger
than the first opening width, each of the bottom edge portions having a second depth that is larger than the first depth,
and the bottom middle portion having a third depth that is same as the first depth.
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