| US 7,557,400 B2 | ||
| Semiconductor device in which capacitance of a MOS capacitor is complemented with the capacitance of a wiring capacitor | ||
| Osamu Wada, Yokohama (Japan); Hiroaki Nakano, Yokohama (Japan); Hiroshi Ito, Yokohama (Japan); Toshimasa Namekawa, Tokyo (Japan); and Atsushi Nakayama, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Feb. 02, 2007, as Appl. No. 11/670,605. | ||
| Claims priority of application No. 2006-026782 (JP), filed on Feb. 03, 2006. | ||
| Prior Publication US 2007/0181918 A1, Aug. 09, 2007 | ||
| Int. Cl. H01L 27/108 (2006.01); H01L 29/00 (2006.01) | ||
| U.S. Cl. 257—312 [257/307; 257/532] | 12 Claims |

| 1. A semiconductor device comprising:
a MOS capacitor in which a drain region and a source region of a MOS structure are commonly connected, and a capacitance is
formed between the commonly connected drain region/source region and a gate electrode of the MOS structure; and
a wiring capacitor which has a first comb-shaped wiring that is formed on said MOS capacitor through an interlayer insulating
film, is connected to the gate electrode of said MOS capacitor, and has projecting portions projecting like comb teeth and
a second comb-shaped wiring that is formed on said MOS capacitor through the interlayer insulating film, is arranged across
an inter-line insulating film from the first comb-shaped wiring, is connected to the drain region and source region, and has
projecting portions projecting like comb teeth,
wherein the projecting portions of the second comb-shaped wiring are arranged alternately with the projecting portions of
the first comb-shaped wiring and arranged perpendicularly to a channel direction connecting the drain region and source region
of said MOS capacitor, and
the MOS structure has a first conductivity type well formed on a second conductivity type semiconductor substrate, second
conductivity type diffusion layers serving as the drain region and the source region which are selectively formed in the surface
of the first conductivity type well, a gate insulating film provided on a region between the second conductivity type diffusion
layers, the gate electrode provided on the gate insulating film, and a first conductivity type diffusion layer for applying
a voltage to a back gate which is formed in the first conductivity type well so as to surround the second conductivity type
diffusion layers.
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