| US 7,557,046 B1 | ||
| Systems and methods for interconnect metallization using a stop-etch layer | ||
| John V. Veliadis, Midlothian, Va. (US) | ||
| Assigned to Northrop Grumman Systems Corporation, Los Angeles, Calif. (US) | ||
| Filed on Oct. 23, 2006, as Appl. No. 11/584,990. | ||
| Int. Cl. H01L 21/302 (2006.01); H01L 21/461 (2006.01) | ||
| U.S. Cl. 438—740 [438/618; 257/E21.17; 257/E21.091; 257/E21.218; 257/E21.229; 257/E21.246] | 29 Claims |
| 1. A method for performing a single lithography step interconnect metallization using a stop-etch layer comprising:
depositing a stop-etch layer over the entire surface of a semiconductor device;
depositing an interconnect metallization material over the stop-etch layer;
performing a single lithography step to pattern a mask over the interconnect metallization material;
etching the interconnect metallization material in non-masked areas to form a hole through the interconnect metallization
material, where the etching is blocked by the stop-etch layer; and
partially removing the stop-etch layer from said semiconductor device.
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