| US 7,556,899 B2 | ||
| System for controlling an overlay, method for controlling overlay, and method for manufacturing a semiconductor device | ||
| Makoto Ikeda, Kanagawa (Japan); Shoichi Harakawa, Kanagawa (Japan); and Takuya Kono, Kanagawa (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Mar. 27, 2006, as Appl. No. 11/389,114. | ||
| Claims priority of application No. P2005-096186 (JP), filed on Mar. 29, 2005. | ||
| Prior Publication US 2006/0265686 A1, Nov. 23, 2006 | ||
| Int. Cl. G03F 9/00 (2006.01); G06F 19/00 (2006.01) | ||
| U.S. Cl. 430—22 [430/30; 382/151; 700/121; 716/19] | 20 Claims |
| 1. A method for manufacturing a semiconductor device, comprising:
sequentially delineating a plurality of underlying patterns of underlying layers below a target layer on a reference semiconductor
substrate;
inspecting an overlay between the target layer and each of the underlying layers;
providing a corrected control set value by:
obtaining a processing data string describing a name of an exposure process for the target layer and an original control set
value of overlays by an exposure tool between a target pattern in the target layer and the underlying patterns in the underlying
layers;
obtaining a plurality of inspection data strings describing a plurality of names of a plurality of inspection processes and
a plurality of inspection values determined by the inspection processes, the inspection processes inspecting respective overlays
between the target and the underlying patterns;
creating a correction data table by combining the processing data string and each of the inspection data strings using a combining
condition table, the combining condition table describing a relationship between the exposure process and each of the inspection
processes; and
calculating the corrected control set value of the exposure tool based on the inspection values of the correction data table;
sequentially delineating the underlying patterns in respective underlying layers on the target semiconductor substrate; and
transferring a pattern of the target layer onto the target semiconductor substrate by the exposure tool, using the corrected
control set value.
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