| US 7,395,288 B2 | ||
| Seed generating circuit, random number generating circuit, semiconductor integrated circuit, IC card, and information terminal equipment | ||
| Shinobu Fujita, Kanagawa-ken (Japan); and Tetsuro Iwamura, Kanagawa-ken (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jan. 22, 2004, as Appl. No. 10/761,326. | ||
| Claims priority of application No. 2003-019732 (JP), filed on Jan. 29, 2003. | ||
| Prior Publication US 2004/0213407 A1, Oct. 28, 2004 | ||
| Int. Cl. G06F 7/02 (2006.01) | ||
| U.S. Cl. 708—251 | 17 Claims |
| 1. A seed generating circuit comprising:
an oscillating circuit which oscillates continuously or intermittently, and which outputs a digital data sequence;
a smoothing circuit which outputs time series data by controlling appearance frequencies of “0” and “1” in the digital data
sequence outputted from the oscillating circuit; and
a postprocessing circuit which generates one-bit seed by a computation using a plurality of bits included in the time series
data, wherein
the oscillating circuit has a first exclusive OR computing circuit, a first inverter circuit, a second exclusive OR computing
circuit, and a second inverter circuit, coupled in series in this order,
data are given to one of input ends of the first exclusive OR computing circuit and to one of input ends of the second exclusive
OR computing circuit, respectively, and
the oscillating circuit oscillates when the data inputted to the first and second exclusive OR computing circuits have a specific
combination.
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