| US 7,394,695 B2 | ||
| Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells | ||
| Ken Takeuchi, Tokyo (Japan); Tomoharu Tanaka, Yokohama (Japan); and Noboru Shibata, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Minato-ku, Tokyo (Japan) | ||
| Filed on Aug. 29, 2006, as Appl. No. 11/511,488. | ||
| Application 11/511488 is a division of application No. 10/073999, filed on Feb. 14, 2002, granted, now 7,177,196. | ||
| Application 10/073999 is a division of application No. 09/667610, filed on Sep. 22, 2000, granted, now 6,373,746. | ||
| Claims priority of application No. 11-275327 (JP), filed on Sep. 28, 1999; and application No. 11-345299 (JP), filed on Dec. 03, 1999. | ||
| Prior Publication US 2007/0058433 A1, Mar. 15, 2007 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 16/04 (2006.01) | ||
| U.S. Cl. 365—185.17 [365/185.21; 365/185.22; 365/185.28] | 24 Claims |
| 1. A nonvolatile semiconductor memory comprising:
a first string line including a first memory cell and a first select transistor connected in series;
a second string line including a second memory cell and a second select transistor connected in series;
a first bit line connected to said first string line;
a second bit line connected to said second string line, being extended to a direction different from a direction in which
the first bit line is extended;
a common node connected to one ends of said first and second bit lines; and
a common latch circuit connected to said common node, wherein first program data of said first memory cell is latched in said
common latch circuit and second program data of said second memory cell is held by said second bit line, during a verify read
of said first memory cell is executed.
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