| US 7,394,691 B2 | ||
| Semiconductor memory device which prevents destruction of data | ||
| Noboru Shibata, Kawasaki (Japan); and Hiroshi Sukegawa, Tokyo (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Aug. 03, 2006, as Appl. No. 11/498,142. | ||
| Claims priority of application No. 2005-234719 (JP), filed on Aug. 12, 2005. | ||
| Prior Publication US 2007/0035997 A1, Feb. 15, 2007 | ||
| Int. Cl. G11C 11/34 (2006.01); G11C 7/00 (2006.01); G11C 29/00 (2006.01) | ||
| U.S. Cl. 365—185.09 [365/185.24; 365/2; 714/773] | 20 Claims |
| 1. A semiconductor memory device comprising:
a memory cell array in which a plurality of memory cells are arranged in a matrix form, each memory cell being connected with
a word line and a bit line and storing n values (n is a natural number which is not smaller than 3);
a write section which writes n-valued data in the memory cell having k values (k<n) stored therein;
a read section which sets a potential of the word line and reads data from the memory cell in the memory cell array; and
a control section which changes the potential of the word line supplied to the read section at the time of reading the k-valued
data when data read by the read section includes an uncorrectable error.
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