| US 7,394,680 B2 | ||
| Resistance change memory device having a variable resistance element with a recording layer electrode served as a cation source in a write or erase mode | ||
| Haruki Toda, Yokohama (Japan); and Koichi Kubo, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jun. 12, 2007, as Appl. No. 11/761,391. | ||
| Prior Publication US 2007/0285966 A1, Dec. 13, 2007 | ||
| Int. Cl. G11C 11/00 (2006.01) | ||
| U.S. Cl. 365—148 [365/163; 365/230.03] | 22 Claims |
| 1. A resistance change memory device comprising:
a semiconductor substrate;
at least one cell array, in which memory cells are arranged, formed above the semiconductor substrate, each the memory cell
having a stack structure of a variable resistance element and an access element, the variable resistance element storing a
high resistance state or a low resistance state in a non-volatile manner, the access element having such an off-state resistance
value in a certain voltage range that is ten times or more as high as that in a select state; and
a read/write circuit formed on the semiconductor substrate as underlying the cell array for data reading and data writing
in communication with the cell array, wherein
the variable resistance element comprises:
a recording layer formed of a composite compound containing at least one transition element and a cavity site for housing
a cation ion; and
electrodes formed on the opposite sides of the recording layer, one of the electrodes serving as a cation source in a write
or erase mode for supplying a cation to the recording layer to be housed in the cavity site therein.
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