| US 7,394,302 B2 | ||
| Semiconductor circuit, operating method for the same, and delay time control system circuit | ||
| Takayoshi Shimazawa, Kawasaki (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Apr. 14, 2005, as Appl. No. 11/105,486. | ||
| Claims priority of application No. 2004-365568 (JP), filed on Dec. 17, 2004. | ||
| Prior Publication US 2006/0132212 A1, Jun. 22, 2006 | ||
| Int. Cl. H03H 11/26 (2006.01) | ||
| U.S. Cl. 327—277 [327/276; 327/261] | 11 Claims |
| 1. A semiconductor circuit connected between an input pad and an output pad of a primitive cell for an automatic routing tool,
comprising:
a first buffer connected between the input pad and the output pad; and
a plurality of capacitances connectable in parallel between a fixed potential and a current flow path positioned between an
output terminal of the first buffer and the output pad,
a second buffer positioned between the input pad and the output pad and connected in parallel to the first buffer and which
provides a driving force different from that of the first buffer;
wherein
a connection between each of the plurality of capacitances and the output pad is controlled, and
a connection between the output terminal of the first buffer and the output pad and a connection between the output terminal
of the second buffer and the output pad are respectively controlled.
|