an MIS transistor including a gate electrode located to intersect a device region of a semiconductor substrate isolated by a device isolation region; source and drain regions provided in the semiconductor substrate at both sides of the gate electrode; and elevated source and drain located above the source and drain regions, the elevated source and drain having a facet along an edge of the device isolation region, and the gate electrode having a first portion located in a device region and a second portion located at a boundary between the device isolation region and the device region,

a gate length of the second portion being about (D1+E1 )/D1 of the gate length of the first portion, D1 being a junction depth of the source and drain where the facet is not formed, and E1 being a length from an upper face of the elevated source and drain to a surface of the semiconductor substrate where the facet is not formed.