| US 7,394,119 B2 | ||
| Metal oxide semiconductor (MOS) type semiconductor device and having improved stability against soft errors | ||
| Hironobu Fukui, Kawasaki (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Mar. 26, 2004, as Appl. No. 10/811,107. | ||
| Claims priority of application No. 2003-399895 (JP), filed on Nov. 28, 2003. | ||
| Prior Publication US 2005/0116361 A1, Jun. 02, 2005 | ||
| Int. Cl. H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/062 (2006.01); H01L 31/113 (2006.01); H01L 31/119 (2006.01) | ||
| U.S. Cl. 257—288 [257/E27.098] | 6 Claims |
| 1. A semiconductor device having a metal oxide semiconductor (MOS) type transistor structure, comprising:
an additional load capacitance that is formed at a part of the semiconductor device, which is vulnerable to soft errors;
wherein the formation of the additional load capacitance is performed such that a first well region that is formed immediately
below the first diffusion layer region is made to have a higher concentration than a second well region; and
wherein an impurity concentration at a junction interface between the first well region with the higher concentration and
the first diffusion layer region is set at 5×1018 to 1019/cm3, and an impurity concentration at a junction interface between the second well region and a second diffusion layer region
which is the diffusion layer regions except for the first diffusion layer region is set at 1018/cm3.
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