| US 7,393,748 B2 | ||
| Method of fabricating a semiconductor memory device | ||
| Fumitaka Arai, Yokohama (Japan); Toshiyuki Enda, Zushi (Japan); Hiroyoshi Tanimoto, Yokohama (Japan); Naoki Kusunoki, Yokohama (Japan); Nobutoshi Aoki, Yokohama (Japan); Riichiro Shirota, Fujisawa (Japan); Hiroshi Watanabe, Yokohama (Japan); and Takamitsu Ishihara, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Dec. 12, 2006, as Appl. No. 11/609,614. | ||
| Claims priority of application No. 2005-359072 (JP), filed on Dec. 13, 2005. | ||
| Prior Publication US 2007/0138536 A1, Jun. 21, 2007 | ||
| Int. Cl. H01L 21/33 (2006.01) | ||
| U.S. Cl. 438—258 [438/266; 257/315] | 17 Claims |
| 1. A method of fabricating a semiconductor memory device with a memory cell array, in which a plurality of memory cells are
connected in series and select gate transistors are disposed at both ends thereof, each memory cell having a floating gate
and a control gate stacked thereabove, comprising:
forming first impurity-doped layers on a semiconductor layer of a first conductivity type formed over a semiconductor substrate
of the first conductivity type with a first insulating film interposed therebetween, the first impurity-doped layers being
of a second conductivity type and serving as channel regions of the select gate transistors;
etching the semiconductor layer, on which a floating gate-use electrode material film is formed with a gate insulating film
interposed therebetween, to form stripe-shaped device formation areas;
forming a control gate-use electrode material film on the floating gate-use electrode material film with an inter-gate dielectric
film interposed therebetween;
selectively etching the control gate-use electrode material film as to penetrate the floating gate-use electrode material
film, thereby forming floating gates and control gates of the memory cells and gate electrodes of the select gate transistors;
forming a second insulating film to be buried between the respective memory cells and between the select gate transistors
and the memory cells and cover the side walls of the openings at bit line and source line contact portions; and
forming second impurity-doped layers of the first conductivity type on the semiconductor layer at the bit line and source
line contact portions.
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