forming a gate insulating film on a semiconductor substrate;

forming a floating gate film on the gate insulating film;

selectively removing a part of the floating gate film so as to define a plurality of floating gates;

depositing a first interlayer insulating film across the entire surface of the semiconductor substrate so as to fill a gap between the floating gates;

removing a part of the first interlayer insulating film so as to expose top surfaces of the floating gates by chemical polishing;

depositing an inter-gate insulating film on the top surfaces of the floating gates;

removing the inter-gate insulating film in an area other than a memory cell transistor area so as to expose the floating gate;

depositing a mask insulating film on the inter-gate insulating film and the exposed floating gate;

forming a device isolation trench in a region for device isolation;

depositing a buried insulating film across the entire surface of the semiconductor substrate including the device isolation trench;

removing the mask insulating film;

forming a control gate film on the inter-gate insulating film and the exposed floating gate;

selectively etching a part of the control gate film so as to define a plurality of control gates and to expose the inter-gate insulating film;

further depositing a second interlayer insulating film across the entire surface of the semiconductor substrate so as to fill a gap between the control gates; and

forming an isolation trench between the memory cell transistor area and a peripheral transistor area,

wherein the control gate is shared by a plurality of memory cell transistors arranged along a row direction, the inter-gate insulating film is shared by a plurality of memory cell transistors arranged along a column direction and is separated from an adjacent inter-gate insulating film by one of the device isolation trench.