| US 7,555,670 B2 | ||
| Clocking architecture using a bidirectional clock port | ||
| Ravindran Mohanavelu, Folsom, Calif. (US); Aaron K. Martin, El Dorado Hills, Calif. (US); Dawson Kesling, Davis, Calif. (US); Joe Salmon, Placerville, Calif. (US); and Mamun Ur Rashid, Folsom, Calif. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Oct. 26, 2005, as Appl. No. 11/260,019. | ||
| Prior Publication US 2007/0091712 A1, Apr. 26, 2007 | ||
| Int. Cl. G06F 1/04 (2006.01); G11C 8/00 (2006.01) | ||
| U.S. Cl. 713—600 [713/500; 711/167; 365/233.11; 365/233.12] | 18 Claims |
| 1. A chip comprising:
a bidirectional clock port, the bidirectional clock port statically configured to either receive or transmit a clock signal
for two or more chips;
a first port to receive data;
a second port to repeat at least a portion of the received data from the first port via a data transmitter at the second port;
an input/output (I/O) port to provide an interface for configuration information; and
a switching element coupled with the I/O port, the switching element to select a clock signal for a transmit clock tree responsive,
at least in part, to the configuration information.
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