US 7,555,633 B1
Instruction cache prefetch based on trace cache eviction
Gregory William Smaus, Austin, Tex. (US); and Mitchell Alsup, Austin, Tex. (US)
Assigned to Advanced Micro Devices, Inc., Sunnyvale, Calif. (US)
Filed on Nov. 03, 2003, as Appl. No. 10/700,033.
Int. Cl. G06F 15/00 (2006.01); G06F 9/30 (2006.01); G06F 9/40 (2006.01)
U.S. Cl. 712—207 23 Claims
OG exemplary drawing
 
15. A method, comprising:
evicting a trace from a trace cache; and
prefetching a line of instructions into an instruction cache from a system memory in response to said evicting;
wherein the system memory is distinct from the instruction cache and the trace cache;
wherein the line of instructions prefetched from the system memory is dependent on contents of the trace evicted from the trace cache;
wherein the line of instructions is not currently needed for execution, and wherein the line of instructions is prefetched in anticipation of instructions included in the evicted trace being re-executed.