| US 7,555,423 B2 | ||
| Emulation processor interconnection architecture | ||
| William F. Beausoleil, Hopewell Jct, N.Y. (US); Mitchell G. Poplack, San Jose, Calif. (US); Steven T Comfort, Poughkeepsie, N.Y. (US); and Beshara Elmufdi, Sunnyvale, Calif. (US) | ||
| Assigned to Quickturn Design Systems, Inc., San Jose, Calif. (US) | ||
| Filed on Dec. 29, 2005, as Appl. No. 11/321,201. | ||
| Claims priority of provisional application 60/648976, filed on Jan. 31, 2005. | ||
| Prior Publication US 2006/0190237 A1, Aug. 24, 2006 | ||
| Int. Cl. G06F 9/455 (2006.01); G06F 9/45 (2006.01) | ||
| U.S. Cl. 703—23 [703/28; 716/5] | 10 Claims |
| 1. A system for interconnecting processors in a processor-based hardware design verification system, comprising:
a plurality of interconnected clusters of emulation processors, each cluster of the plurality of interconnected clusters comprising:
a plurality of emulation processors that can execute Boolean equations;
a shared data storage array, said shared data storage array comprising a plurality of data storage structures, each emulation
processor of the plurality of emulation processors within said cluster capable of communicating with each data storage structure
within said shared data storage array;
an array of outputs, each output of the array of outputs generated from each emulation processor of the plurality of emulation
processors;
a plurality of multiplexer arrays, each multiplexer array of the plurality of multiplexer arrays comprising:
a plurality of multiplexers for selecting output signals;
a plurality of input arrays, each input array of the plurality of input arrays containing just one output from each cluster
of the plurality of interconnected clusters; and
a plurality of outputs, each output of the plurality of outputs communicating with a unique shared data storage array of each
cluster of the plurality of interconnected clusters.
|