| US 7,555,121 B2 | ||
| Methods and apparatus for implementing a cryptography engine | ||
| Terry K. Tham, San Jose, Calif. (US); and Errol Lai, Mountain View, Calif. (US) | ||
| Assigned to Broadcom Corporation, Irvine, Calif. (US) | ||
| Filed on Oct. 29, 2004, as Appl. No. 10/977,317. | ||
| Application 10/977317 is a division of application No. 09/948203, filed on Sep. 06, 2001. | ||
| Claims priority of provisional application 60/235190, filed on Sep. 25, 2000. | ||
| Prior Publication US 2005/0063538 A1, Mar. 24, 2005 | ||
| Int. Cl. H04K 1/00 (2006.01); H04L 9/00 (2006.01); H04L 9/38 (2006.01); G06F 12/14 (2006.01); H04L 9/32 (2006.01) | ||
| U.S. Cl. 380—29 [380/30; 380/28; 380/259; 380/37; 713/168; 713/171; 713/189; 713/190; 714/724] | 7 Claims |
| 1. A cryptography accelerator for performing cryptography operations, the cryptography accelerator comprising:
a block cipher engine, operating at a first clock rate;
surrounding logic coupled to the block cipher engine,the surrounding logic operating at a second clock rate different from
the first clock rate; and
a frequency synchronizer coupled to the block cipher engine and the surrounding logic, the frequency synchronizer configured
to compensate for clock rate differences between the block cipher engine and surrounding logic by generating a synchronization
pulse when a start signal is received from the surrounding logic, wherein the synchronization pulse is generated at the second
clock rate and wherein the synchronization pulse is one cycle of the first clock wide and is centered around an edge of the
first clock.
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