| US 7,554,875 B2 | ||
| Bus structure, memory chip and integrated circuit | ||
| Christian Sichert, Munich (Germany); Rainer Bartenschlager, Kaufbeuren (Germany); and Jens Polney, Munich (Germany) | ||
| Assigned to Qimonda AG, Munich (Germany) | ||
| Filed on Jan. 31, 2007, as Appl. No. 11/700,399. | ||
| Prior Publication US 2008/0181044 A1, Jul. 31, 2008 | ||
| Int. Cl. G11C 8/00 (2006.01) | ||
| U.S. Cl. 365—230.06 [365/198; 365/191] | 23 Claims |
| 13. A memory chip, comprising:
a memory array with a plurality of memory array terminals;
a plurality of driver circuits, each driver circuit comprising an input for a first signal, a terminal for an output signal
and a further terminal coupled to one memory array terminal of the plurality of memory array terminals such that each driver
circuit of the plurality of driver circuits is coupled to a respective memory array terminal of the plurality of memory array
terminals, wherein each driver circuit is capable of providing the output signal at the terminal upon receipt of the first
signal;
a parallel data bus comprising a plurality of output signal lines and a receiving end being connectable to a target component,
each output signal line extending at least from the receiving end to the terminal of a different one of the plurality of driver
circuits such that a length of the output signal line between the receiving end and the respective driver circuit of the plurality
of driver circuits decreases in a connection order among the plurality of driver circuits; and
a signal line coupled to each of the inputs of the driver circuits of the plurality of driver circuits in the connection order;
wherein the memory chip is integrated into a single chip.
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