| US 7,554,866 B2 | ||
| Circuit and method of controlling input/output sense amplifier of a semiconductor memory device | ||
| Jang-won Moon, Anyang-si (Korea, Republic of); and Jong-Hyoung Lim, Hwaseong-si (Korea, Republic of) | ||
| Assigned to Samsung Electroncis Co., Ltd., (Korea, Republic of) | ||
| Filed on Jun. 21, 2007, as Appl. No. 11/820,836. | ||
| Claims priority of application No. 10-2006-0063366 (KR), filed on Jul. 06, 2006. | ||
| Prior Publication US 2008/0008011 A1, Jan. 10, 2008 | ||
| Int. Cl. G11C 7/00 (2006.01); G11C 7/10 (2006.01); H03F 3/45 (2006.01) | ||
| U.S. Cl. 365—205 [365/189.05; 365/191; 365/193; 365/196; 327/57] | 9 Claims |
| 1. An input/output sense amplifier (IOSA) control circuit comprising:
an auto pulse generator configured to generate an auto pulse signal having a first pulse shape; and
a latch enable signal generating circuit configured to generate a first latch enable signal having a second pulse shape that
activates a latch in the IOSA in response to the auto pulse signal in normal mode, and configured to generate a second latch
enable signal having a level shape for activating the latch in response to a write enable bar signal in test mode.
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