| US 7,554,860 B1 | ||
| Nonvolatile memory integrated circuit having assembly buffer and bit-line driver, and method of operation thereof | ||
| Poongyeub Lee, Cupertino, Calif. (US); and Ming-Chi Liu, Sunnyvale, Calif. (US) | ||
| Assigned to Actel Corporation, Mountain View, Calif. (US) | ||
| Filed on Sep. 21, 2007, as Appl. No. 11/859,073. | ||
| Int. Cl. G11C 7/10 (2006.01) | ||
| U.S. Cl. 365—189.05 [365/154; 365/205] | 7 Claims |
| 1. An assembly buffer and bitline driver circuit including:
a data line;
a column line;
a bit line;
a Y-select line;
two low-voltage inverters cross-coupled to form an assembly buffer latch, the assembly buffer latch having a first output
coupled to the column line and a second complementary output;
a first switch coupled between the data line and the column line, the first switch having a control element coupled to the
Y-select line;
a second switch coupled between the column line and the bit line, the second switch having a control element coupled to a
column select signal line;
two high-voltage inverters cross-coupled to form a bitline driver latch, the bitline driver latch having a first output coupled
to the bit line and a second complementary output;
a first low-voltage n-channel MOS data-transfer transistor coupled between the output of the first high-voltage inverter and
ground, a gate of the first low-voltage n-channel MOS transistor coupled to the complementary output of the assembly buffer
latch; and
a second low-voltage n-channel MOS data-transfer transistor coupled between the output of the second high-voltage inverter
and ground, a gate of the second low-voltage n-channel MOS transistor coupled to the output of the assembly buffer latch.
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