| US 7,554,376 B2 | ||
| Offset correcting method, offset correcting circuit, and electronic volume | ||
| Tatsuya Kishii, Iwata (Japan) | ||
| Assigned to Yamaha Corporation, Hamamatsu-shi (Japan) | ||
| Filed on Jun. 13, 2007, as Appl. No. 11/818,131. | ||
| Application 11/818131 is a continuation of application No. 10/890057, filed on Jul. 13, 2004, granted, now 7,245,169. | ||
| Claims priority of application No. P.2003-196563 (JP), filed on Jul. 14, 2003. | ||
| Prior Publication US 2007/0247208 A1, Oct. 25, 2007 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H03F 3/45 (2006.01) | ||
| U.S. Cl. 327—307 [330/261; 330/260; 327/142] | 4 Claims |
| 1. An offset correcting circuit comprising:
an amplifying unit including an offset adjusting unit that adjusts an offset of the amplifying unit;
an offset determining unit that detects the offset of the amplifying unit and outputs a signal for correcting the offset of
the amplifying unit; and
a power-ON detecting unit that detects a power ON signal to output a reset signal which causes the offset determining unit
to start correcting the offset, wherein
the offset determining unit includes a comparing unit that compares an output of the amplifying unit with a reference value,
and a counter that increases or decreases a count value in response to an output of the comparing unit, and
the offset adjusting unit includes a bias varying portion having a plurality of transistors connected in parallel with each
other and which varies a bias of the amplifying unit by changing on/off states of the plurality of transistors based on the
count value of the counter, thereby adjusting the offset.
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