| US 7,554,205 B2 | ||
| Flip-chip type semiconductor device | ||
| Yoichiro Kurita, Kawasaki (Japan); Rieka Ouchi, Kawasaki (Japan); Takashi Miyazaki, Kawasaki (Japan); and Toshiyuki Yamada, Kawasaki (Japan) | ||
| Assigned to NEC Electronics Corporation, Kawasaki-Shi (Japan) | ||
| Filed on May 11, 2007, as Appl. No. 11/798,224. | ||
| Application 11/798224 is a division of application No. 10/919411, filed on Aug. 17, 2004, granted, now 7,238,548. | ||
| Claims priority of application No. 2003-295067 (JP), filed on Aug. 19, 2003. | ||
| Prior Publication US 2007/0216035 A1, Sep. 20, 2007 | ||
| Int. Cl. H01L 23/48 (2006.01) | ||
| U.S. Cl. 257—778 [257/787; 257/E23.116] | 9 Claims |
| 1. A semiconductor package comprising:
a semiconductor device having a plurality of electrode terminals provided and arranged on a top surface of said semiconductor
device, and a sealing resin layer formed on the top surface of said semiconductor device such that said electrode terminals
are completely covered with said sealing resin layer; and
a substrate having a plurality of electrode terminals provided and arranged on a top surface of said substrate, the arrangement
of the electrode terminals of said substrate having a mirror image relationship with respect to the arrangement of the electrode
terminals of said semiconductor device,
wherein said semiconductor device is mounted on said substrate such that the electrode terminals of said substrate penetrate
into said sealing resin layer, and are directly connected to the respective electrode terminals of said semiconductor device,
wherein said semiconductor device further includes a protective layer formed on the top surface of said semiconductor device
except for the electrode terminals of said semiconductor device, with said protective layer being completely covered with
said sealing resin layer,
a top surface of the electrode terminals of said semiconductor device being lower than a top surface of said protective layer.
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