| US 7,554,202 B2 | ||
| Semiconductor integrated circuit device | ||
| Yasushi Koubuchi, Kokubunji (Japan); Koichi Nagasawa, Koganei (Japan); Masahiro Moniwa, Sayama (Japan); Youhei Yamada, Kodaira (Japan); and Toshifumi Takeda, Tachikawa (Japan) | ||
| Assigned to Renesas Technology Corp, Tokyo (Japan) | ||
| Filed on Jul. 27, 2007, as Appl. No. 11/878,843. | ||
| Application 10/956159 is a division of application No. 10/619039, filed on Jul. 14, 2003, granted, now 7,274,074. | ||
| Application 09/846260 is a division of application No. 09/050416, filed on Mar. 31, 1998, granted, now 6,261,883. | ||
| Application 11/878843 is a continuation of application No. 11/878666, filed on Jul. 26, 2007. | ||
| Application 11/878666 is a continuation of application No. 11/802450, filed on May 23, 2007, granted, now 7,474,003. | ||
| Application 11/802450 is a continuation of application No. 10/956159, filed on Oct. 04, 2004, granted, now 7,250,682. | ||
| Application 10/619039 is a continuation of application No. 10/075246, filed on Feb. 15, 2002, granted, now 6,664,642. | ||
| Application 10/075246 is a continuation of application No. 09/846260, filed on May 02, 2001, granted, now 6,433,438. | ||
| Claims priority of application No. 9-81013 (JP), filed on May 31, 1997; and application No. 10-33388 (JP), filed on Feb. 16, 1998. | ||
| Prior Publication US 2008/0017990 A1, Jan. 24, 2008 | ||
| Int. Cl. H01L 29/76 (2006.01) | ||
| U.S. Cl. 257—776 [257/758; 257/183; 257/197; 257/762; 257/766] | 30 Claims |
| 1. A semiconductor integrated circuit device comprising:
trenches formed in a semiconductor substrate and defining an active region and dummy regions not functioning as an element;
a semiconductor element formed in the active region and arranged at an internal circuit area;
element isolation insulating films filled in the trenches;
interconnections formed over the substrate and electrically connected to the semiconductor element;
first dummy interconnections formed over the substrate and not functioning as an element;
wherein the first dummy interconnections are formed by the same level layer as the interconnections;
a first insulating film formed over the first dummy interconnections and the interconnections;
an external terminal formed over the first insulating film,
wherein the dummy regions are regularly arranged at a scribing area and at the internal circuit area, respectively,
wherein the first dummy interconnections are regularly arranged at the internal circuit area and under the external terminal,
respectively.
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