| US 7,554,199 B2 | ||
| Substrate for evaluation | ||
| Takenori Narita, Mito (Japan); Masaki Ito, Hamura (Japan); and Kenji Sameshima, Hachioji (Japan) | ||
| Assigned to Consortium for Advanced Semiconductor Materials and Related Technologies, Tokyo (Japan) | ||
| Filed on Nov. 13, 2006, as Appl. No. 11/598,537. | ||
| Claims priority of application No. 2005-336586 (JP), filed on Nov. 22, 2005; and application No. 2006-017212 (JP), filed on Jan. 26, 2006. | ||
| Prior Publication US 2007/0117386 A1, May 24, 2007 | ||
| Int. Cl. H01L 23/52 (2006.01) | ||
| U.S. Cl. 257—752 [257/762; 438/692; 438/687; 438/626] | 13 Claims |
| 1. An evaluation substrate for evaluating a condition of a CMP that is employed for configuring a semiconductor device having
a plurality of wirings in a vertical direction, said evaluation substrate comprising:
a substrate;
a first groove formed in said substrate;
a second groove formed in said substrate; and
a material of the wirings provided in said first groove and said second groove, a depth of said first groove differing from
that of said second groove, an upper boundary defining said first groove being arranged substantially level with a corresponding
upper boundary defining said second groove wherein said first groove is equivalent to a groove for configuring said wiring,
and said material of said wiring has a single one-layer structure which extends over a surface of said substrate and is contiguous
with the material in said first groove and said second groove, and said substrate not having another conductive layer besides
said single one-layer structure.
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