| US 7,554,182 B2 | ||
| Semiconductor device and package, and method of manufacturer therefor | ||
| Kenichi Shirasaka, Hamamatsu (Japan); and Hiroshi Saitoh, Iwata-gun (Japan) | ||
| Assigned to Yamaha Corporation, Shizuoka-ken (Japan) | ||
| Filed on Sep. 07, 2006, as Appl. No. 11/516,705. | ||
| Application 11/516705 is a continuation of application No. 10/120391, filed on Apr. 12, 2002, granted, now 7,170,149. | ||
| Claims priority of application No. 2001-115381 (JP), filed on Apr. 13, 2001; and application No. 2002-013159 (JP), filed on Jan. 22, 2002. | ||
| Prior Publication US 2007/0001275 A1, Jan. 04, 2007 | ||
| Int. Cl. H01L 23/495 (2006.01) | ||
| U.S. Cl. 257—676 [257/787; 257/666; 257/692; 438/126; 438/127] | 9 Claims |
| 1. A semiconductor package comprising:
a plurality of outer leads arranged in an outer periphery of a bottom of said package, said outer leads being exposed to an
exterior of said package and adapted to provide electrical connections with a substrate; and
a plurality of inner leads that extend from a periphery of a stage, and integrally formed with the stage, for supporting a
semiconductor chip, a distal end of each inner lead being positioned lower than the stage, said distal ends of said inner
leads being exposed to said exterior on said bottom of said package and arranged inwardly of said outer leads with respect
to said periphery of said bottom of said package, said distal ends of said inner leads are adapted to provide electrical connections
with the substrate.
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