| US 7,554,176 B2 | ||
| Integrated circuits having a multi-layer structure with a seal ring | ||
| Hiroshi Naito, Kokubu (Japan) | ||
| Assigned to Yamaha Corporation, Shizuoka-ken (Japan) | ||
| Filed on Mar. 24, 2005, as Appl. No. 11/88,969. | ||
| Application 11/088969 is a continuation in part of application No. 11/039956, filed on Jan. 24, 2005, granted, now 7,193,296. | ||
| Claims priority of application No. 2004-094621 (JP), filed on Mar. 29, 2004; application No. 2004-094622 (JP), filed on Mar. 29, 2004; and application No. 2005-075554 (JP), filed on Mar. 16, 2005. | ||
| Prior Publication US 2005/0218501 A1, Oct. 06, 2005 | ||
| Int. Cl. H01L 23/544 (2006.01); H01L 21/4763 (2006.01) | ||
| U.S. Cl. 257—620 [257/700; 257/751; 257/758; 257/E23.019; 257/E21.019; 438/622; 438/623] | 8 Claims |
| 1. A semiconductor wafer on which a plurality of IC regions partitioned by scribing regions are formed to realize ICs having multilayer structures, and a plurality of seal rings are formed in peripheral areas of the ICs, wherein with respect to each of the IC regions, an uppermost wiring layer is formed together with a continuous metal layer that is formed in the seal ring, a planar insulating layer is formed to cover the metal layer, the IC, and the scribing region, and a passivation film is formed on the planar insulating layer, wherein the continuous metal layer formed in the seal ring includes a plurality of levels and extends into the planar insulating layer and towards each of the IC region and the scribing region. |