| US 7,554,163 B2 | ||
| Semiconductor device | ||
| Takayuki Yamada, Toyama (Japan); Atsuhiro Kajiya, Hyogo (Japan); and Satoshi Ishikura, Osaka (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Jul. 07, 2006, as Appl. No. 11/481,909. | ||
| Claims priority of application No. 2005-198328 (JP), filed on Jul. 07, 2005. | ||
| Prior Publication US 2007/0007603 A1, Jan. 11, 2007 | ||
| Int. Cl. H01L 29/76 (2006.01) | ||
| U.S. Cl. 257—393 [257/391; 257/392; 257/903; 257/E21.661; 257/E27.098; 257/E27.099] | 20 Claims |
| 1. A semiconductor device comprising:
a first MIS transistor and a second MIS transistor,
wherein said first MIS transistor includes:
a first source/drain region formed in a first semiconductor region surrounded by an isolation region in a semiconductor substrate;
and
a first gate electrode formed on said first semiconductor region and having a first gate length and a first gate width,
said second MIS transistor includes:
a second source/drain region formed in a second semiconductor region surrounded by said isolation region in said semiconductor
substrate; and
a second gate electrode formed on said second semiconductor region and having a second gate length and a second gate width,
said first gate electrode and said second gate electrode are formed integrally extending in a gate width direction, and connected
with each other, thereby constituting a single gate line,
said first gate width is larger than said second gate width,
said first semiconductor region and said second semiconductor region are separated from each other by said isolation region,
and sandwich said isolation region in the gate width direction, and
said first semiconductor region has a smaller width along a gate length direction than said second semiconductor region, wherein
said first MIS transistor and said second MIS transistor are included in an SRAM, and wherein said first MIS transistor and
said second MIS transistor are access transistors.
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