| US 7,554,152 B1 | ||
| Versatile system for integrated sense transistor | ||
| Paul Ranucci, Tucson, Ariz. (US); and Robert Labicane, Tucson, Ariz. (US) | ||
| Assigned to National Semiconductor Corporation, Santa Clara, Calif. (US) | ||
| Filed on Jan. 11, 2006, as Appl. No. 11/330,049. | ||
| Int. Cl. H01L 29/788 (2006.01) | ||
| U.S. Cl. 257—316 [257/288; 438/257] | 20 Claims |
| 1. A method of producing a sense transistor operatively associated with a power transistor, the method comprising the steps
of:
providing a power transistor, having a plurality of alternating source and drain structures, with a plurality of gate structures
interposed there between;
at a desired location, forming a sense transistor by providing an isolated portion of either a drain or source structure,
wherein the sense transistor has a same local bulk potential as the power transistor; and
coupling some circuitry, external to the power transistor, to the isolated portion.
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