| US 7,553,732 B1 | ||
| Integration scheme for constrained SEG growth on poly during raised S/D processing | ||
| David E. Brown, Pleasant Valley, N.Y. (US); and Scott D. Luning, Poughkeepsie, N.Y. (US) | ||
| Assigned to Advanced Micro Devices, Inc., Sunnyvale, Calif. (US) | ||
| Filed on Jun. 13, 2005, as Appl. No. 11/150,923. | ||
| Int. Cl. H01L 21/336 (2006.01) | ||
| U.S. Cl. 438—300 [257/E21.619] | 20 Claims |
| 1. A method of manufacturing a semiconductor device comprising:
forming a gate structure overlying a semiconductor substrate comprising a gate stack and a sacrificial layer;
forming a sidewall spacer adjacent to the gate structure;
selectively removing the sacrificial layer after forming the sidewall spacer to expose a surface of the gate stack; and
forming an epitaxial layer overlying an active region adjacent the gate structure and overlying the surface of the first layer
of the gate structure.
|