| US 7,392,331 B2 | ||
| System and method for transmitting data packets in a computer system having a memory hub architecture | ||
| Ralph James, Andover, Minn. (US); and Joe Jeddeloh, Shoreview, Minn. (US) | ||
| Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
| Filed on Aug. 31, 2004, as Appl. No. 10/931,326. | ||
| Prior Publication US 2006/0047891 A1, Mar. 02, 2006 | ||
| Int. Cl. G06F 3/00 (2006.01) | ||
| U.S. Cl. 710—36 [710/20] | 35 Claims |
| 1. In a memory system having a plurality of memory modules each of which contains a memory hub connected to a plurality of
memory devices, a system in at least one memory hub for receiving data packets through a first upstream link from a downstream
memory module and the memory devices connected to the memory hub and for transmitting the received data packets through a
second upstream link to either an upstream memory module or a controller, the system comprising:
an upstream reception port coupled to the first upstream link and operable to receive data packets from the downstream memory
module;
a bypass bus coupled to the upstream reception port and operable to receive the data packets from the upstream reception port
and to transport the data packets;
a temporary storage coupled to the upstream reception port and operable to receive the data packets from the upstream reception
port;
an upstream transmission port coupled to the second upstream link, the second upstream link being isolated from the first
upstream link;
a bypass multiplexer for selectively coupling the upstream transmission port to each of a core logic circuit, the temporary
storage, and the bypass bus; and
a breakpoint logic circuit coupled to the bypass multiplexer and operable to switch the bypass multiplexer to selectively
connect the upstream transmission port to each of the core logic circuit, the bypass bus, and the temporary storage.
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