US 11,683,935 B2
NOR flash memory
Masaru Yano, Kanagawa (JP)
Assigned to Winbond Electronics Corp., Taichung (TW)
Filed by Winbond Electronics Corp., Taichung (TW)
Filed on Aug. 24, 2018, as Appl. No. 16/111,237.
Claims priority of application No. JP2017-160921 (JP), filed on Aug. 24, 2017.
Prior Publication US 2019/0067325 A1, Feb. 28, 2019
Int. Cl. G11C 16/04 (2006.01); H10B 43/27 (2023.01); H10B 41/00 (2023.01); H10B 43/30 (2023.01); H10B 43/35 (2023.01); H10B 43/50 (2023.01); G11C 16/06 (2006.01); G11C 11/56 (2006.01); G11C 16/10 (2006.01)
CPC H10B 43/27 (2023.02) [G11C 16/0466 (2013.01); H10B 41/00 (2023.02); H10B 43/30 (2023.02); H10B 43/35 (2023.02); H10B 43/50 (2023.02); G11C 11/5671 (2013.01); G11C 16/06 (2013.01); G11C 16/10 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A NOR flash memory, comprising:
a substrate;
a source line formed on a surface of the substrate for providing a reference potential;
a pillar part extending in a vertical direction from the surface of the substrate, and comprising a conductive semiconductor material, wherein the pillar part has a top end above a bottom end, and the bottom end of the pillar part is electrically connected to the reference potential via the source line;
a bit line disposed on the top end of the pillar part, and electrically connected to the pillar part via a contact hole;
a set of the NOR flash memory including a plurality of NOR flash memory cells and a plurality of selecting transistors, wherein the plurality of NOR flash memory cells of the set are connected to the bit line in parallel, and each of the plurality of selecting transistors of the set is connected between the source line and a corresponding one of the plurality of NOR flash memory cells; and
an interlayer insulating film formed between a first one of the plurality of NOR flash memory cells and a first one of the plurality of selecting transistors, wherein the pillar part has a first portion between a top surface of the interlayer insulating film and the top end of the pillar part, and the pillar part has a second portion between a bottom surface of the interlayer insulating film and the bottom end of the pillar part;
wherein each of the plurality of selecting transistors comprises:
an insulating film formed by surrounding the second portion of the pillar part; and
a selecting gate formed below the interlayer insulating film to surround the insulating film,
wherein each of the plurality of NOR flash memory cells is connected in series to a corresponding one including the first one of the selecting transistors, and comprises:
a charge accumulating part formed by surrounding the first portion of the pillar part, wherein the charge accumulating part includes a material different from that of the insulating film; and
a control gate formed on the interlayer insulating film so as to surround the charge accumulating part.