US 11,683,925 B2
Semiconductor device
Jung Gil Yang, Suwon-si (KR); Sun Wook Kim, Suwon-si (KR); Jun Beom Park, Suwon-si (KR); Tae Young Kim, Suwon-si (KR); and Geum Jong Bae, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jul. 28, 2021, as Appl. No. 17/387,192.
Application 17/387,192 is a continuation of application No. 16/722,081, filed on Dec. 20, 2019, granted, now 11,107,822.
Claims priority of application No. 10-2019-0057758 (KR), filed on May 17, 2019.
Prior Publication US 2021/0358923 A1, Nov. 18, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 29/786 (2006.01); H01L 29/775 (2006.01); B82Y 10/00 (2011.01); H01L 27/02 (2006.01); H01L 29/423 (2006.01); H10B 10/00 (2023.01)
CPC H10B 10/125 (2023.02) [H01L 23/528 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first fin type pattern extending lengthwise in a first direction;
a second fin type pattern extending lengthwise in the first direction and spaced apart from the first fin type pattern in a second direction from the first direction;
a first gate pattern and a second gate pattern intersecting the first fin type pattern and the second fin type pattern;
a third gate pattern and a fourth gate pattern intersecting the first fin type pattern between the first gate pattern and the second gate pattern;
a fifth gate pattern and a sixth gate pattern intersecting the second fin type pattern between the first gate pattern and the second gate pattern;
a first semiconductor pattern between the fifth gate pattern and the sixth gate pattern, on the second fin type pattern; and
a gate cut structure separating the third and fourth gate patterns and the fifth and sixth gate patterns,
wherein the first semiconductor pattern is electrically floating.